The present invention relates to plasma processing apparatuses for processing substrate-like specimens, such as semiconductor wafers, loaded on stages disposed in processing chambers inside vacuum vessels, using plasma formed in the processing chambers, and in particular, relates to a plasma processing apparatus for etching a processing-target film layer on a film structure preliminarily formed on a surface of a specimen by heating the specimen.
In order to satisfy requirements for reduced power consumption and increased memory capacities, further refined semiconductor devices have been prevailed and three-dimensional device structures have been widely promoted. Due to complicated, steric structures, devices having three dimensional structures, where film layers configuring circuits have conventionally been etched in longitudinal directions (depth directions of device circuit structures), tend to be frequently etched in lateral directions for manufacturing.
For such etching in lateral directions, wet processing through which processing-target film layers are processed and etched in a chemical solution has been implemented. Such wet processing is based on isotropic etching where the processing advances not only in a single direction, but also evenly on an entire circumference. When such wet processing is implemented in further refined circuits configured with narrower line widths, although such circuits are expected to be required in reality in future, such a problem that a structure including sidewalls of grooves on circuit patterns could be collapsed due to surface tension of a chemical solution is predicted to be revealed.
For this reason, as a technology for performing such isotropic etching, it is estimated that conventional wet processing should be replaced with dry processing that require no chemical solution. As a technology for achieving such isotropic dry etching at higher precision, an adsorption and desorption style etching method has been devised.
With this technology, a reaction layer having a minute thickness is first formed through a chemical reaction, between a material of a surface of a film layer and active particles, occurred by allowing the particles having higher reactivity, such as radicals generated in plasma, to be adsorbed on the surface of the etching-target film layer on a plurality of film structures including masks preliminarily disposed on surfaces of specimens, such as semiconductor wafers, for forming circuits (adsorption process). Next, thermal energy is added onto the reaction layer (to heat the layer) to allow this reaction layer to be evaporated, desorbed, and removed (desorption process). To etch at a desired amount, the adsorption and desorption processes are alternately repeated.
With this technology, upon the reaction layer reaches a certain thickness through adsorption processes, the reaction layer can prevent radicals from being reached to an interface between the processing-target film layer and the reaction layer, thus growth of the reaction layer is quickly reduced. Accordingly, it is thought that, even if radical flux is unevenly distributed inside a complex pattern shape, a reaction layer having a uniform thickness can be formed by adsorbing for an enough period, and an amount of etching can be uniform without depending on the pattern shape.
In such processes, a thickness of a reaction layer is limited in a range where atoms or molecules that can react with radicals adhered onto the atoms or molecules as a result of exposure to the radicals generated from plasma are present in a material configuring a surface of a processing-target film layer. Therefore, since it is predicted that, in a cycle of an adsorption process and a desorption process, an amount of etching can be controlled at or below a level of several nanometers, it is expected that an etching process where an amount of process can be adjusted with dimensional accuracy at or below several nanometers is achieved.
A technology described in JP-A-2013-522884, is conventionally known as an example of such a technology. In JP-A-2013-522884, an apparatus including a processing chamber coupled with a plasma source and a heating source, and a substrate support disposed inside the processing chamber is disclosed. The apparatus forms plasma through the plasma source with a gas supplied in the chamber to form an oxide layer, which is derived from reaction products, on a surface of a substrate, such as a wafer, loaded onto the substrate support, and heats the substrate so that a temperature of the substrate rises with heat radiated or conducted from the heating source by means of bringing the wafer close to the heating source, or another means, to sublimate oxides.
This conventionally known technology discloses a configuration where any plasma source that is based on inductive coupling, capacitive coupling, or similar coupling is used, and the heating source is disposed inside the substrate support, and where, during plasma is formed, radio-frequency (RF) power having a certain frequency is supplied onto an electrode disposed inside the substrate support to form bias potential above an upper surface of the substrate.